IBIS Macromodel Task Group

Meeting date: 05 August 2008

Members (asterisk for those attending):
  Ambrish Varma, Cadence Design Systems
  Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
  Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
* Brad Brim, Sigrity
  Brad Griffin, Cadence Design Systems
* David Banas, Xilinx
  Donald Telian, consultant
  Doug White, Cisco Systems
  Essaid Bensoudane, ST Microelectronics
* Fangyi Rao, Agilent
  Ganesh Narayanaswamy, ST Micro
  Gang Kang, Sigrity
  Hemant Shah, Cadence Design Systems
* Ian Dodd, Agilent
  Joe Abler, IBM
* John Angulo, Mentor Graphics
  John Shields, Mentor Graphics
  Ken Willis, Cadence Design Systems
  Kumar
  Lance Wang, Cadence Design Systems
  Luis Boluna, Cisco Systems
  Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
  Mike Steinberger, SiSoft
  Mustansir Fanaswalla, Xilinx
  Patrick O'Halloran, Tiburon Design Automation
  Paul Fernando, NCSU
* Pavani Jella, TI
  Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
  Ray Comeau, Cadence Design Systems
  Richard Mellitz, Intel
  Richard Ward, Texas Instruments
  Sam Chitwood, Sigrity
  Sanjeev Gupta, Agilent
  Shangli Wu, Cadence Design Systems
* Sid Singh, Extreme Networks
  Stephen Scearce, Cisco Systems
  Steve Pytel, Ansoft
  Syed Huq, Cisco Systems
  Syed Sadeghi, ST Micro
  Terry Jernberg, Cadence Design Systems
  Todd Westerhoff, SiSoft
  Vikas Gupta, Xilinx
  Vuk Borich, Agilent
* Walter Katz, SiSoft
  Zhen Mu, Cadence Design Systems


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Opens:

- none

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Call for patent disclosure:

- No one declared a patent.


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Review of ARs:

- EDA vendors review IBIS-SPICE presented 22 Jul 2008

- Mike L send link to IBIS-SPICE document
  - Done

- Todd and Michael M contact Synopsys about HSPICE legal issues
  - TBD

- David Banas report Xilinx position on LTI assumption for SerDes
  - No update

- Arpad:  Write parameter passing syntax proposal (BIRD draft)
          for *-AMS models in IBIS that is consistent with the
          parameter passing syntax of the AMI models
          - TBD

- TBD:    Propose a parameter passing syntax for the SPICE
          - [External ...] also?
          - TBD

- Arpad:  Review the documentation (annotation) in the macro libraries.
          - Deferred until a demand arises or we have nothing else to do

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New Discussion:

There are no new changes on the IBIS-SPICE document.

Arpad's IBIS-EBD improvements:
- A [View] instantiates the entire description of a module
- Can only have one [View] at a time
- Nodes on the circuits inside the [View]s must represent all xnet pins
- Arpad: Why do we need to talk about SPICE?
- Walter: There are 2 parts to what we need:
  - High level connectivity description
  - Specific circuit elements for modeling
- We could use any language for the 2nd part
- Arpad: Many will use HSPICE format
- Walter: Some would like to use a linear HSPICE subset
  - This is "IBIS-SPICE"
  - Should be easy to convert to any other language
- Walter: It must easy to:
  - Make models
  - Consume models
- Arpad: How do we instantiate things that have models?
- Walter described an example of [Reference Designator List]
- John: [Extended Nets] indicates what goes together
  - Different sets of interconnect might be model at different frequencies
  - Walter: Can have stages within subckts
    - Different types of models used for 3 subckts tied together
- Mike L: We could use name=value on [View] line for future expansion
  - Walter: Agree
    - Could have "Corner=" for example
    - But we need to get something out soon
- Arpad: the example shows a TX connecting to RX on the same module
- John: Using refdes to denote which side of interconnect for same pin names
  - We have to tell the EDA tool which side is connected
  - Walter: A reference mapping file is used
- John: [mPin] could be [Pin]
  - Walter: Have to distinguish module pins from totally internal pins
- John: Maybe EBD could be extended by BIRD to do this
  - Walter: Document becomes difficult to read, but no other objection
  - Must try to avoid conditionals (if this then that) of ICM
- Arpad: Calls inside [View] look like netlisting
  - Could uncoupled models have 1 line instead of 2?
  - Walter: May not want to call all terminals of sim ckt
  - Arpad: Could look inside ckt file to see nodes
  - Walter: The file  may be large
- Mike: Could give extended nets names instead of pin lists
  - Walter: Puts onus on external circuit file to observe order
    - Coupled circuits have different conventions
  - Arpad: May not need to give pinlists at all
    - Could impicitly always use [EMD Pin] list in order
    - John: May have many nets, sometimes want a subset
    - Arpad: Why give the same pin list over and over?
    - Bob: Pin order might be different for different languages
- Arpad: Do we need a netlisting system with subckts at this level?
  - No

Next meeting: 12 August 2008 12:00pm PT

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